The prospect of replacing the amorphous SiO₂ dielectric by amorphous or epitaxially grown high-K (high dielectric constant) insulators for future devices is a challenging task. Advanced gate dielectrics have gained enormous attention, because the technology roadmap proposed by the SIA predicts the need for gate dielectrics with a thickness of less than 15 Å in the near future - a thickness range where large tunneling currents will the exclude use of SiO₂ (figure 1).

   MEIS has been proven to be a powerful technique not only to study the composition of various high-K materials (see the table below, i.e., ZrO₂, HfO₂, La₂O₃, Y₂O₃ as well as their silicates) but also to investigate relevant atomic transport processes and the formation of interfacial layers between the high-K film and the substrate.

   Depth profiles of the isotope constituents of these films obtained from MEIS, complemented by TEM and other techniques, are valuable tools to understand, optimize, and model the electrical characteristics of such thin film structures.

   Presently our work on high-K dielectrics is performed in collaboration with LUCENT Technologies, North Carolina State University, and University of Texas at Austin. It is supported in the frame of the SRC and NSF.